1. Field of the Invention
The present invention relates to a semiconductor device including two types of MIS transistors and a manufacturing method of the same, and particularly is suitable for application to a semiconductor device using a high dielectric constant material for a gate insulating film of one of the MIS transistors.
2. Description of the Related Art
In recent years, as a transistor whose gate leakage current is small and power consumption is low, a MIS transistor using a gate insulating film made of a high dielectric constant material (hereinafter abbreviated only as a high dielectric constant transistor) attracts attention. However, this high dielectric constant transistor is not suitable for high-speed operation at a low threshold voltage since the threshold voltage shifts to the high-voltage side.
On the other hand, a MIS transistor using a gate insulating film made of a silicon oxide or a silicon oxynitride (hereinafter abbreviated only as a SiO-based transistor) enables high-speed operation since the threshold voltage can be made low although its power consumption is higher than that of the high dielectric constant transistor.
Hence, it is proposed that as a semiconductor device, the high dielectric constant transistor and the SiO-based transistor are mixedly mounted, and the former transistor is mounted on a portion which does not require high-speed operation but requires low power consumption, whereas the latter transistor is mounted on a portion which requires high-speed operation although its power consumption is relatively high. More specifically, as in Patent Documents 1 and 2, after a first gate insulating film made of a silicon oxide is first formed on the entire surface of a substrate, the first insulating film is patterned to be left only on a first active region. Then, after a second gate insulating film made of a high-melting point material is formed on the entire surface of the substrate, including the first gate insulating film, the second gate insulating film is patterned to be left only on a second active region. By this series of process steps, the first gate insulating film and the second gate insulating film can be separately formed on the first active region and the second active region, respectively.
(Patent Document 1)
Japanese Patent Application Laid-open No. 2000-188338
(Patent Document 2)
Japanese Patent Application Laid-open No. 2003-23100
However, in the case of Patent Documents 1 and 2, when the second gate insulating film is patterned, surface damage due to etching is inevitably caused to the first gate insulating film when the second gate insulating film on the first gate insulating film is removed by etching. If the transistors are formed in this state, satisfactory electric properties of the transistors (for example, reduction in gate leakage current, operating life extension, and so on) cannot be obtained.